The present inventions are related to systems and methods for data storage, and more particularly to systems and methods for governing the life cycle of a solid state drive and/or flash memory device.
Flash memory devices have been used in a variety of systems where stored information must be maintained even when power to the system is lost. Such flash memory devices can be grouped together with a system controller to implement what are commonly referred to as solid state drives. FIG. 1 depicts an exemplary, prior art solid state drive 100 that includes a number of flash memory devices 112, 114, 122, 124, 132, 134, 142, 144 each coupled to a controller 150 via lanes 110, 120, 130, 140. Each of lanes 110, 120, 130, 140 includes a combination of control signals and data signals that allow for accessing the respective flash memory devices.
Each of flash memory devices 112, 114, 122, 124, 132, 134, 142, 144 include a number of readable and writable memory cells that are arranged in storage blocks. The memory cells may be charged to two or more distinct voltage levels that represent one or more data bits. Each time a memory cell is written, the performance of the cell degrades. This degradation progresses until the cell is no longer reliably written. Because of this, flash memory devices are typically rated based upon the number of program/erase cycles expected from the device. As an example, a single level cell capable of storing a single bit of data may be expected to withstand 100K program/erase cycles before becoming unreliable. In contrast, a multi-level cell capable of storing two bits of data may be expected to withstand 10K program/erase cycles before becoming unreliable.
In an effort to extend the life cycle of a flash memory device, various approaches for wear leveling have been developed that seek to assure that storage blocks in a flash memory device degrade at approximately the same rate. These approaches generally require moving data around in the device to level the number of writes across the blocks in the device. As part of this wear leveling, flash memory devices may be over provisioned with one or more storage blocks in excess of the storage blocks that appear accessible from the flash memory interface. A graphical depiction of this over provisioning is provided in FIG. 2. As shown, the memory space of a flash memory device 200 is implemented as a number of blocks 205, with each block having a number of memory cells. The addressable memory space of flash memory device 200 is represented by ‘m’, and the actual number of blocks is represented by ‘n’. The difference between m and n (i.e., n−m) is the over provisioning of blocks in memory device 200. In operation, where one block becomes unreliable, data from that block is moved to a reliable block and the block from which the data was moved is marked as unusable. When this occurs the value of n is decreased to recognize the newly identified unreliable data block. Eventually, as more and more blocks are rendered unreliable, n becomes equal to m. From this point, when another block is rendered unreliable, flash memory device 200 no longer offers its full usable memory space and is identified as unusable. Flash memory device 200 and/or the solid state drive in which it is deployed may then be replaced. Such failure can be unpredictable, and in one or more cases unrecoverable.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for augmenting the operation of solid state drives and/or flash memory devices to provide for enhanced control of failure.